Generally, semiconductor manufacturing processes are classified into a pre-process which is called a batch fabrication process (FAB) and a post-process which is called a packaging/test process. The pre-process is to set up circuit devices in a silicon substrate through a plurality of processes, such as diffusion, photo, etching, ion-implantation and thin film processes. After testing the characteristics of each device, which is formed in a wafer by the pre-processes, the post-process includes performing a burn-in test as part of a final test on the unit device and includes the processes of sawing, bonding and molding the wafer by unit devices and a trim/form process. Here, the burn-in test is performed in order to increase the productivity of the final test. The burn-in test is carried out at a temperature of approximately 125° C. and a pattern test is thereafter carried out in a range of approximately 60° C. to 75° C. after the burn-in test. After lowering the temperature to a room temperature, the result of the test is sorted. The time required in the burn-in test may vary, depending on the use of the device. The equipment for semiconductor fabrication for the burn-in test is classified into first to third generation MBTs (Memory Burn-in Tester). The first generation MBT is a monitoring burn-in test capable of monitoring the burn-in results, the second generation MBT has a fast operation with a data management capability, and the third generation MBT is TDBI (Test During Burn-in) which includes the features of the first and second generation MBTs and further measures the characteristics of devices themselves.
As semiconductor chips become more and more integrated, each cell becomes more and more miniaturized. Due to the integration with small cell size, the operating voltage is also reduced. In case of the DRAM (Dynamic random access memory), an internal power supply is generated by an external power supply provided from an external circuit; however, the external power supply can undergo a variation in voltage level because of noise and other environmental effects. Therefore, an internal voltage generating circuit should be designed in order to generate a stable voltage regardless of the deterioration of the exterior voltage.
FIG. 1 is a block diagram of a conventional internal voltage generating circuit. Referring to FIG. 1, a band gap reference circuit 10 produces a power supply voltage Vbg which is insensitive to a PVT (Process, Voltage, and Temperature) fluctuation. This power supply voltage Vbg is applied to a reference voltage generating circuit 20 to generate a reference voltage Vref and an internal voltage generating circuit 60 generates an internal voltage based on the reference voltage Vref.
The internal voltage generating circuit 60 includes a standby internal voltage generating circuit 30, an active internal voltage generating circuit 40, and an internal voltage control circuit 50. The standby internal voltage generating circuit 30, which is always active during the standby and active operations, is employed to stabilize an early voltage level with a low drivability. The active internal voltage generating circuit 40 is designed to supply the large driving force needed in the active mode by a plurality of active internal voltage generating circuits that are formed to provide sufficient driving force. When the semiconductor device operates, the internal voltage control circuit 50 outputs an active signal Act to activate the active internal voltage generating circuit 40.
A plurality of the active internal voltage generating circuits 40 are employed in the semiconductor device and are respectively activated depending on the corresponding active signals Act.
FIG. 2 is a block diagram of the internal voltage generating circuit in FIG. 1. For the sake of convenience, a high voltage power supply VPP, which is used for activating a word line, is illustrated as one of the internal voltage sources in the semiconductor device.
As described above, when the semiconductor device operates, that is, when the semiconductor device is in an active mode, the active internal voltage generating circuit 40 operates in order to obtain a large amount of the driving force. A high voltage generating unit 40a in FIG. 2 corresponds to the active internal voltage generating circuit 40 in FIG. 1. On the other hand, the standby internal voltage generating circuit 30 illustrated in FIG. 1, which functions in the standby or active mode, corresponds to a standby internal high voltage generating circuit 30a in FIG. 2.
Referring to FIG. 2, a high voltage generating circuit 60a includes an internal voltage controller 50a and a high voltage generating unit 40a. Different internal control signals pwrup, ratv, rpcg and cke are activated in the active mode and input to the internal voltage controller 50a. To produce an active signal Act, the internal voltage controller 50a receives the power-up signal pwrup which is activated in the active mode, a RAS (Row Address Strobe) active signal ratv which is activated in a row active mode, a precharge signal rpcg which is activated in a precharge mode and a clock active signal cke for a low power operation.
The high voltage generating unit 40a includes a high voltage detecting unit 42a and a high voltage pumping unit 44a. A reference voltage Vref is applied to the high voltage detecting unit 42a and the high voltage detecting unit 42a is activated in response to the active signal Act. The high voltage pumping unit 44a, which receives an output signal PEE of the high voltage detecting unit 42a, carries out a charge pumping operation.
FIG. 3 is a circuit diagram of the high voltage detecting unit 42a of FIG. 2. Referring to FIG. 3, the high voltage detecting unit 42a includes resistors R1 and R2 for dividing a high voltage power supply VPP which is a feedback voltage from the high voltage pumping unit 44a, a comparator 46a having a current mirror amplifier structure operated in response to the active signal Act, and an inverter INV2 inverting an output signal of the comparator 46a. 
The high voltage detecting unit 42a compares the divided voltage of the resistors R1 and R2 with the reference voltage Vref. When the divided voltage of the resistors R1 and R2 is higher than the reference voltage Vref, the high voltage detecting unit 42a outputs the output signal PEE with a high level. To the contrary, when the divided voltage of the resistors R1 and R2 is lower than the reference voltage Vref, the high voltage detecting unit 42a outputs the output signal PEE with a low level.
In other words, the active signal Act output from the internal voltage controller 50a of FIG. 2 activates the high voltage detecting unit 42a and the high voltage detecting unit 42a outputs the output signal PEE. The high voltage pumping unit 44a supplies the internal power, which is needed in the active mode, through the charge pumping operation in response to the output signal PEE.
FIG. 4 is a circuit diagram of the internal voltage controller of FIG. 2. Referring to FIG. 4, the internal voltage controller 50a includes: a PMOS transistor P1 having a gate to receive the power-up signal pwrup during the power-up operation; a PMOS transistor P2 to receive the precharge signal rpcg activated in the precharge mode; an inverter INV4 for receiving and inverting the RAS active signal ratv in the row active mode; an NMOS transistor N1 having a gate to receive an output signal of the inverter INV4; a latch circuit having two inverters INV5 and INV6 for latching a logic level on node Nod1; an inverter INV8 for receiving and inverting an output signal of the latch circuit; an inverter INV7 for receiving and inverting the clock active signal cke for the low power operation; and a NOR gate NOR2 to receive output signals of the inverter INV8 and the inverter INV7.
FIGS. 5A and 5B are timing charts illustrating the operating characteristics of the internal voltage controller 50a of FIG. 4. FIG. 5A is a timing chart illustrating the operating characteristics at the time of a normal operation. Referring to FIG. 5A, the active signal Act is kept in a high level in an active section in response to the internal control signals cke, rats and rpcg. Thereafter, the activate signal Act is kept in a low level in a standby section in response to the transition of the precharge signal rpcg which goes from a low level to a high level. Therefore, the high voltage generating unit 40a of FIG. 2, which receives the active signal Act, is driven in the active section and does not function/operate in the standby section. The active section denotes a time period that the semiconductor device is active. The standby section denotes a time period that the semiconductor device is in a standby mode.
FIG. 5B is a timing chart illustrating the operating characteristics at the time of a test operation. Referring to FIG. 5B, the active signal Act is kept in a high level in the active section only at the time of the test operation. That is, the high voltage generating unit 40a does not operate in the standby section.
However, at the time of TDBI (Test During Burn-in) test operation, the repeated access at a high voltage and high temperature can cause a large amount of leakage current to exponentially increase and then cause a fast voltage drop of the internal voltage in the standby section in which the internal voltage is kept in a relatively low level. The fast dropping of the internal voltage produces greater leakage paths, causing the semiconductor device to be burned by the highly increased temperature or a O/S (Open/Short) failure. In this case, the breakdown of the internal elements is caused so that a latch-up phenomenon is created. As a result, it is impossible to perform the stable test operation and the reliability of the semiconductor chips deteriorates.